Western Digital is typically thought of as a traditional HDD manufacturer more than an SSD firm, but the company’s joint NAND flash venture with Toshiba is designed to change that. Today, that work appears to have paid off in a significant way with two separate announcements. First, WD claims that it will begin sampling 96-layer NAND flash by the end of this year, with early commercial volumes ramping up in 2018. That’s a significant achievement, given that Intel just announced commercial shipments of 64-layer NAND earlier this week, but the situation isn’t quite as rosy as the company makes it sound.
As of February 2017, Toshiba and WD hadn’t yet shipped their 64-layer Bit Cost Scaling (BiCS) NAND flash technology. They may have done so now, but there’s clearly a lead time between when companies are announcing these targets and when they’re actually hitting them.
QLC NAND stores four bits per cell
This leads us to the second announcement, and arguably the more surprising of the two. Western Digital is also claiming that it has a valid roadmap for commercializing QLC (Quad-Level Cell) NAND.
This has previously been thought to be extremely difficult. The problem with storing more data per cell of NAND is that you have to store more threshold voltage values in every cell. An SLC cell is either a 0 or a 1 — two states and one threshold voltage that determines which state the cell is in. MLC NAND has four states (each bit can be either a 0 or a 1, with two bits per cell) and three threshold voltages.
TLC NAND, which faced ramp-up issues of its own, has three bits of data per cell, eight total states, and seven threshold voltages. And QLC NAND will have four bits of data per cell, 16 states, and 15 threshold voltages. But the process of programming NAND flash makes it easy for reads and writes to one cell to change the values of adjacent cells, and this problem only gets worse the more values you need to store in every cell.
To make QLC work properly, WD has adopted a “thick” process node for its 3D NAND, Anandtech notes. That implies this NAND is built on at least 40nm as opposed to the 20nm processes that were generally used for the last generation of conventional 2D planar NAND. The company hasn’t disclosed any information on program/erase cycles, but storing four bits of data per cell is expected to leave chips with a 100-150 P/E endurance rating, barely a tenth of the already-low 1000 P/E cycles that TLC NAND is typically rated for. This could limit QLC’s use to portable storage devices or storage products that are expected to function primarily as read drives (write once read many, or WORM for short).
Western Digital has stated it will chip 3D ICs at up to 1Tb capacity over the next few years, a substantial increase over the 256Gb 3D NAND chips that are currently the industry standard.
Let’s block ads! (Why?)