Last year, at Intel Architecture Day, the company unveiled a unique chip called Lakefield. Lakefield blends a single high-end Ice Lake CPU core with four low-power cores built on a new iteration of Intel’s low-power architecture, codenamed Tremont. This is the first time we’ve seen Intel debut a blended CPU with cores from the Atom and Core families sharing space on the same silicon. Lakefield is connected together via Intel’s 3D Foveros interconnect and is intended for products like the recently announced dual-screen Surface Neo.
From 2008 to 2011, Intel’s Atom product line kept the same architecture and focused on lowering power consumption. Bonnell and Saltwell (45nm and 32nm) were followed by Silvermont, which was used in Intel’s Bay Trail tablet family. Airmont, Goldmont, and Goldmont Plus all followed. Goldmont+ made a few changes to Goldmont to improve performance, and Tremont includes its own improvements on top of these.
The goal with Tremont was to improve Atom performance enough to allow it to overlap with Core, without compromising the small die size and lower power that Atom is known for. The goal is for Tremont to provide a 30 percent performance uplift relative to Goldmont Plus.
Intel has not talked about Tremont’s die size or power consumption, beyond emphasizing that Lakefield deploys four Tremont cores and one Sunny Cove CPU core, while being compared to 7W CPUs overall. It’s likely that Intel had to make some tradeoffs on die or power to boost performance this much, but it also means that Tremont cores should be fairly solid. Based on the historic performance of the Atom family, Tremont should be closing in on “big core” IPC from some years ago, and may land between Nehalem and Ivy Bridge in at least some workloads — at least, when comparing strictly in terms of IPC. Clock rates also matter, and we have no idea what the clock speeds are on Lakefield or for the Tremont architecture.
What we do know is that the Sunny Cove-class branch predictor has been brought over, after being tweaked for the smaller CPU. There’s no penalty for L1 prediction and a smaller penalty for L2 than in previous generations.
Tremont is a 6-wide decode CPU paired with a four-wide allocation/dispatch engine. This is a rather odd framing. Typically decode and dispatch are either equally wide or dispatch is actually larger than decode. Part of the reason for this is that Tremont isn’t quite a 6-wide CPU. It’s more like a 3-wide CPU with two identical decoder blocks slapped down side by side. Each of the three-wide decode engines can decode a separate instruction scheme and the decoders can be gated to save power when not in use. Intel also has the option to use just one of the decoders in some products if it wishes to do so. With just one instruction stream, Tremont is only a 3-wide design.
The reason Intel went with this unusual arrangement was to avoid the use of a micro-op cache. A micro-op cache can help keep a wide decoder fed, but it also consumes die area. This design supposedly beat out the micro-op cache method when area, power, and performance were all considered. L1 data cache is up to 32KB now, from 24KB on Goldmont and previous CPUs. There’s support for an LLC that can be inclusive or non-inclusive depending on how Intel wants to configure it. L2 is shared between cores but can be configured between 1.5MB and 4.5MB depending on end-user preference.
There are tweaks to the integer and floating-point sections of the core as well, with a larger out-of-order window, six parallel reservation stations, and a wide execution engine with 3 ALUs, 2 AGUs, a jump and a store data. Execution resources are significantly weaker than Core, but this makes sense — if Lakefield didn’t have some use for a Sunny Cove CPU core, Intel wouldn’t have bothered to build one.
Intel is also introducing a new feature known as Total Memory Encryption, apparently as a further barrier against certain types of physical attacks. Details on how TME will work and what platforms it supports, however, are not currently available. The platform will also support Intel’s Speed Shift technology, in a further shift for Atom relative to Core. Previously, only “big core” CPUs supported capabilities like Speed Shift, which gives the CPU control over its own clock transitions rather than relying on software to handle it.
The expected overlap between Tremont and Sunny Cove’s overall performance and expected capabilities. This only compares the two in single-threaded scenarios and appears to show Tremont hitting about half the power level of Sunny Cove at the lowest end of the graph.
Superficially, Tremont looks like a nice uplift for Atom and the entire low-power Intel CPU family, but there’s a lot we don’t know about this CPU core as far as how it actually performs. Five years ago, Intel’s Atom line was heavily focused on tablets, only to refocus on low-end laptops when the x86 tablet market died. Intel hasn’t announced any broad shipments or availability for Tremont and it isn’t clear if this chip is intended for the same notebook parts. We also don’t have any details on the GPU core or operating clock.
Thus far, Lakefield has only been announced for Surface Neo, and Neo isn’t likely to be a huge volume part. The 30 percent performance uplift looks particularly nice, but we’d like to know more about other aspects of the SoC before rendering an overall verdict. Lakefield is a unique product, but the very factors that make it interesting also make it hard to predict performance. Intel hasn’t built this kind of chip before, so we’ll have to wait a bit and see how everything shakes out.
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