21 May 2020
Cadence Design Systems has announced the availability of 56G long-reach SerDes IP on TSMC’s N7 and N6 process technologies.
Hyperscale computing continues to be the main driver for very high-speed SerDes, and 112G/56G is seen as a key enabler for cloud data centre and optical networking applications. 56G connectivity is particularly important for 5G infrastructure deployment, both in baseband and remote radio head systems.
To address this broader market, Cadence has expanded its PAM4 SerDes portfolio with 56G long-reach SerDes IP on the TSMC N7 and N6 processes delivering optimised power, performance and area (PPA).
The Cadence 56G long-reach SerDes IP offers designers a number of benefits, including:
- Best-in-class 36db+ insertion loss using Cadence’s multi-rate DSP technology
- Industrial temperature range, CPRI data rate support and per-lane PLL are ideal for 5G applications
- 56G long-reach performance has been achieved on N7 test silicon and is compatible with the N6 process
- Fully compliant with the IEEE standard specification
- Programmable power configurations via a unique firmware-controlled adaptive power optimizer, which provides optimal power and performance trade-offs and more efficient system designs based on platform requirements
- Optimal data recovery through the programmable DSP-based architecture
- Improved flexibility enabled by the extended reach capability lets customers use lower cost PCBs and achieve greater flexibility in PCB and system design.
“After being first to market in 2019 with silicon-proven 112G-LR SerDes on TSMC 7nm technology, we have now expanded our offering to include PPA-optimised 56G-LR to address the connectivity needs of the 5G infrastructure and AI/ML market. This PAM4-based 56G-LR SerDes is based on Cadence’s multi-rate DSP technology,” said Rishi Chugh, vice president of product marketing, IP Group at Cadence. “The availability of Cadence’s 56G long-reach SerDes IP accelerates the adoption and deployment of cost-effective 100G and 400G networks.”
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