14 November 2017
Leti, an institute of CEA Tech, together with EV Group (EVG), a supplier of wafer bonding and lithography equipment, have announced the first successful 300-mm wafer-to-wafer direct hybrid bonding with a pitch dimension of just 1µm (micron). This breakthrough also achieved copper pads as small as 500nm.
The copper/oxide hybrid bonding process, a key enabler for 3D high-density IC applications, was demonstrated in Leti’s cleanrooms using EVG’s fully automated GEMINIFB XT fusion wafer bonding system. EVG joined the institute’s 3D Integration Consortium in February 2016.
Vertical stacking of semiconductor devices has become an increasingly viable approach to enabling continuous improvements in device density and performance and wafer-to-wafer bonding is an essential process to enable 3D stacked devices.
Tight alignment and overlay accuracy between the wafers is required to achieve good electrical contact on the bonded wafers, as well as to minimise the interconnect area at the bond interface so that space is made available on the wafer.
The constant reduction in pitches needed to support component roadmaps is driving tighter wafer-to-wafer bonding specifications with each new product generation.
Leti was able to demonstrate that the top and bottom 300-mm wafers were directly bonded in the GEMINI FB XT automated production fusion bonding system, and achieved overlay alignment accuracy to within 195nm (3-sigma) overall, with mean alignment results well centred below 15nm. Post-bake acoustic microscopy scans of the full 300-mm bonded wafer stack as well as specific dies confirmed a defect-free bonding interface for pitches ranging from 1µm to 4µm with optimum copper density.
“To our knowledge, this is the first reported demonstration of sub-1.5µm pitch copper hybrid bonding feasibility,” said Frank Fournel, head of bonding process engineering at Leti. “This latest demonstration represents a real breakthrough and important step forward in enabling the achievement and eventual commercialization of high-density 3D chip stacking.”
“3D integration holds the promise for increased device density and bandwidth as well as lower power consumption for a variety of applications, from next-generation CMOS image sensors and MEMS to high-performance computing,” stated Markus Wimplinger, corporate technology development and IP director at EV Group.
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